The present invention relates generally to a semiconductor memory device and more specifically to an arrangement of sense amplifiers and memory cell arrays in a semiconductor memory device.
It is a continuing goal to make a semiconductor memory device finer in order to provide more memory cells on a single device, decrease chip size and/or reduce manufacturing costs. One such method of decreasing the chip size of a semiconductor memory device, such as a dynamic random access memory (DRAM), is to provide a plurality of cell arrays that have a row of shared sense amplifiers disposed between. Each shared sense amplifier selectively receives data from a bit line pair from one memory cell array or from a bit line pair from the adjacent memory cell array.
Referring now to FIG. 1, a plan view of a conventional semiconductor memory device is set forth in a schematic diagram and given the general reference character 500.
Conventional semiconductor device 500 of FIG. 1 has shared sense amplifiers arranged in a row between adjacent memory cell arrays. Each shared sense amplifier is connected to two bit line pairs (four bit lines).
Conventional semiconductor device 500 consists of cell arrays (521, 522, 523 and 524). Each cell array (521, 522, 523 and 524) has a plurality of bit lines.
Cell array 521 includes bit lines (601 to 624). Bit lines (601 to 624) are arranged in bit line pairs (601-602 to 623-624). Each bit line pair (601-602 to 623-624) includes a bit line and a complementary bit line. Likewise, cell arrays (522 to 524) respectively include bit lines (625 to 648, 649 to 672, and 673 to 696). Bit lines (625 to 648) are arranged in bit line pairs (625-626 to 647-648). Bit lines (649 to 672) are arranged in bit line pairs (649-650 to 671-672). Bit lines (673 to 696) are arranged in bit line pairs (673-674 to 695-696). Likewise, each bit line pair (625-626 to 647-648, 649-650 to 671-672, and 673-674 to 695-696) includes a bit line and a complementary bit line.
Cell array 521 has a row of unshared sense amplifiers (531 to 536) on one side and a row of shared sense amplifiers (537 to 542) on the other side. Bit line pairs (601-602 to 623-624) are respectively, alternatively connected to unshared sense amplifiers (531 to 536) and shared sense amplifiers (537 to 542). More specifically, bit line pair (601-602) is connected to unshared sense amplifier 531, bit line pair (602-603) is connected to shared sense amplifier 537, and so on, and bit line pair (623-624) is connected to shared sense amplifier 542.
Cell array 522 has the row of shared sense amplifiers (537 to 542) on one side and a row of shared sense amplifiers (543 to 548) on the other side. Bit line pairs (625-626 to 647-648) are respectively, alternatively connected to shared sense amplifiers (543 to 548) and shared sense amplifiers (537 to 542). More specifically, bit line pair (625-626) is connected to shared sense amplifier 543, bit line pair (627-628) is connected to shared sense amplifier 537, and so on, and bit line pair (647-648) is connected to shared sense amplifier 542.
Cell array 523 has the row of shared sense amplifiers (543 to 548) on one side and a row of shared sense amplifiers (549 to 554) on the other side. Bit line pairs (649-650 to 671-672) are respectively, alternatively connected to shared sense amplifiers (543 to 548) and shared sense amplifiers (549 to 554). More specifically, bit line pair (649-650) is connected to shared sense amplifier 543, bit line pair (651-652) is connected to shared sense amplifier 549, and so on, and bit line pair (671-672) is connected to shared sense amplifier 554.
Cell array 524 has a row of unshared sense amplifiers (555 to 560) on one side and a row of shared sense amplifiers (549 to 554) on the other side. Bit line pairs (673-674 to 695-696) are respectively, alternatively connected to unshared sense amplifiers (555 to 560) and shared sense amplifiers (549 to 554). More specifically, bit line pair (673-674) is connected to unshared sense amplifier 555, bit line pair (675-676) is connected to shared sense amplifier 549, and so on, and bit line pair (695-696) is connected to shared sense amplifier 554.
Conventional semiconductor device 500 includes sense amplifier drivers (501 to 510).
Unshared sense amplifiers (531 to 533) are connected to sense amplifier driver 501.
Unshared sense amplifiers (534 to 536) are connected to sense amplifier driver 502. Shared sense amplifiers (537 to 539) are connected to sense amplifier driver 503. Shared sense amplifiers (540 to 542) are connected to sense amplifier driver 504. Shared sense amplifiers (543 to 545) are connected to sense amplifier driver 505. Shared sense amplifiers (546 to 548) are connected to sense amplifier driver 506. Shared sense amplifiers (549 to 551) are connected to sense amplifier driver 507. Shared sense amplifiers (552 to 554) are connected to sense amplifier driver 508. Shared sense amplifiers (555 to 557) are connected to sense amplifier driver 509. Shared sense amplifiers (558 to 560) are connected to sense amplifier driver 510.
In semiconductor memory device 500, cell arrays (521 to 524) are conceptualized as (Nxe2x88x921)th to (N+2)th cell arrays, respectively, where N is an integer of 2 or more. Sense amplifier drivers (501 and 502), and unshared sense amplifiers (531 to 536) are conceptualized as a (Nxe2x88x921)th sense amplifier section. Sense amplifier drivers (503 and 504), and shared sense amplifiers (537 to 542) are conceptualized as a Nth sense amplifier section. Sense amplifier drivers (505 and 506), and shared sense amplifiers (543 to 548) are conceptualized as a (N+1)th sense amplifier section. Sense amplifier drivers (507 and 508), and shared sense amplifiers (549 to 554) are conceptualized as a (N+2)th sense amplifier section. Sense amplifier drivers (509 and 510), and unshared sense amplifiers (555 to 560) are conceptualized as a (N+3)th sense amplifier section.
In conventional semiconductor memory device 500, when Nth cell array 522 is activated, for example, Nth sense amplifier section (including sense amplifier drivers (503 and 504) is activated and (N+1)th sense amplifier section (including sense amplifier drivers (505 and 506) is activated. In this way, sense amplifiers (537 to 548) are activated to read data on bit lines (625 to 648) connected to the selected side of sense amplifiers (537 to 548). In FIG. 1, the sense amplifiers (537 to 548) activated when Nth cell array 522 is activated are illustrated with hatching.
In conventional semiconductor memory device 500, each sense amplifier section is configured to include one sense amplifier for every two bit line pairs (four bit lines), so that adjacent sense amplifiers in one sense amplifier section are not connected to adjacent bit lines. Instead adjacent sense amplifiers in each sense amplifier section are electrically separated by two bit lines (one bit line pair).
Also, adjacent sense amplifiers in each sense amplifier section are driven by a different sense amplifier driver (501 to 510). For example, although Nth sense amplifier section includes sense amplifiers (537 to 542), sense amplifiers (537 to 539) are connected to be driven by sense amplifier driver 503 and sense amplifiers (540 to 542) are connected to be driven by sense amplifier driver 504. Such an arrangement of sense amplifiers arranged to be driven by separate sense amplifier drivers is disclosed in Japanese Laid-Open Patent Publication No. Hei 9-45879, entitled xe2x80x9cDynamic RAM.xe2x80x9d
By providing a sense amplifier driver for every other sense amplifier in a sense amplifier section, a sense amplifier driver provides current to every fourth bit line pair. However, in the conventional semiconductor device 500, each sense amplifier in a row of sense amplifiers is activated. Because sense amplifiers are disposed in as narrow pitch as feasibly possible, the noise generated by sense amplifiers upon activation is in a concentrated region. This can cause adverse affects during the sensing operation.
Also, in the conventional semiconductor memory device 500, bit lines (601 to 696) are arranged to span the width of a cell array (521 to 524). Thus, for example, when Nth cell array 522 is activated and bit lines (625 to 648) provide corresponding data values, adjacent bit lines can be affected by xe2x80x9ccross-talk.xe2x80x9d It is noted that an adjacent bit lines are running in parallel for essentially the width of the cell array. Thus, there is a maximum cross-talk between adjacent bit lines. The cross-talk induced noise can have adverse affects on, for example the access speed or data integrity during the operation of reading data.
In light of the above discussion, it would be desirable to provide a semiconductor memory device where the dispersion of sense amplifiers may be such that a large group of adjacent sense amplifiers may not be activated simultaneously. It would also be desirable to provide a semiconductor memory device that may have reduced coupling noise (cross-talk) between adjacent bit lines. It would also be desirable to provide a semiconductor memory device that may have a reduced chip size.
A semiconductor memory device according to the present embodiments may include a plurality of cell arrays and a plurality of sense amplifier sections. Adjacent cell arrays may have a sense amplifier section disposed between. Sense amplifiers within a sense amplifier section may be connected to a bit line that is connected to a plurality of memory cells in more than one of the cell arrays. When a cell array is activated, sense amplifier sections that may be distributed around edges of a plurality of cell arrays may be activated to sense data from the activated cell array. In this way, current may be distributed and noise may be reduced. An activated bit line may be adjacent to a precharged bit line in a non-activated cell array. In this way, cross-talk between activated bit lines may be reduced.
According to one aspect of the embodiments, semiconductor memory device may include a plurality of cell arrays with adjacent cell arrays separated by a row of sense amplifiers. A plurality of bit lines may be included where each bit line may be connected to a plurality of memory cells in each of the plurality of cell arrays. Each bit line of the plurality of bit lines may be connected to a sense amplifier not included in the row of sense amplifiers separating the adjacent cell arrays in the plurality of cell arrays.
According to another aspect of the embodiments, each sense amplifier in the row of sense amplifiers separating adjacent cell arrays is connected to a bit line, separate from the plurality of bit lines, in each of the adjacent cell arrays.
According to another aspect of the embodiments, the plurality of bit lines may be a plurality of complementary bit line pairs
According to another aspect of the embodiments, adjacent ones of the plurality of bit lines may be separated by at least one bit line separate from the plurality of bit lines and that may be connected to a plurality of memory cells in a different cell array from the plurality of cell arrays.
According to another aspect of the embodiments, the semiconductor memory device may be a dynamic random access memory.
According to another aspect of the embodiments, a semiconductor memory device may include a plurality of cell arrays and a plurality of sense amplifier sections. Each cell array may include a plurality of memory cells. Each sense amplifier section may include a plurality of sense amplifiers provided adjacent to one of the plurality of cell arrays. Each sense amplifier may be connected to a bit line that may be connected to memory cells in at least two cell arrays of the plurality of cell arrays.
According to another aspect of the embodiments, the plurality of cell arrays may be disposed in a first direction parallel to the bit line. The plurality of cell arrays may include a first cell array adjacent to a second cell array. The plurality of sense amplifier sections may include a first sense amplifier section on a first side of the first cell array and a second sense amplifier section on a second side of the first cell array and disposed between the first and second cell arrays. When the first cell array is activated, the first and second sense amplifier sections may be activated. When the second cell array is activated, the first and second sense amplifier sections may be activated.
According to another aspect of the embodiments, a semiconductor memory device may include a third sense amplifier section on the opposite side of a second cell array from a second sense amplifier section. When a first cell array is activated, the first, second and third sense amplifier sections may be activated. When the second cell array is activated, the first second and third sense amplifier sections may be activated.
According to another aspect of the embodiments, each sense amplifier section may include a sense amplifier driver coupled to the plurality of sense amplifiers.
According to another aspect of the embodiments, the plurality of cell arrays may include an end cell array. The plurality of sense amplifiers sections may include an end sense amplifier section. A sense amplifier driver in the end sense amplifier section may have a smaller drive strength than the sense amplifier driver in other ones of the plurality of sense amplifier sections.
According to another aspect of the embodiments, each bit line may be a complementary bit line pair. Adjacent sense amplifiers in each of the plurality of sense amplifier sections may be connected to complementary bit line pairs that may be separated by at least three complementary bit line pairs.
According to another aspect of the embodiments, the plurality of cell arrays may include an end cell array. The plurality of sense amplifier sections may include an end sense amplifier sections. The plurality of sense amplifiers in sense amplifier sections disposed between adjacent cell arrays may be shared sense amplifiers. The plurality of sense amplifiers in the end sense amplifier section may be unshared sense amplifiers.
According to another aspect of the embodiments, a semiconductor memory device may include a first cell array and a second cell array. A first sense amplifier section may include a plurality of sense amplifiers on a first side of the first cell array. A second sense amplifier section may include a plurality of sense amplifiers on an opposite side of the first cell array and between the first and second cell array. Each one of the plurality of sense amplifiers in the first sense amplifier section may be electrically connected to a bit line that may be connected to a plurality of memory cells in the first cell array and a plurality of memory cells in the second cell array.
According to another aspect of the embodiments, each one of the plurality of sense amplifiers in the second sense amplifier section may be electrically connected to a bit line that may be connected to a plurality of memory cells in the first cell array and to a separate bit line that may be electrically connected to a plurality of memory cells in the second cell array.
According to another aspect of the embodiments, when the first cell array is active, at least one of the bit lines that is connected to a plurality of memory cells in the first cell array and a plurality of memory cells in the second cell array may be adjacent to a bit line in the second cell array that is in a precharge state.
According to another aspect of the embodiments, when the first cell array is active, the at least one of the bit lines that is connected to a plurality of memory cells in the first cell array and a plurality of memory cells in the second cell array may be adjacent to a bit line in the first cell array that is providing data.
According to another aspect of the embodiments, a third sense amplifier section may include a plurality of sense amplifiers on the opposite side of the second cell array. Each one of the plurality of sense amplifiers in the third sense amplifier section may be electrically connected to a bit line that may be connected to a plurality of memory cells in the first cell array and a plurality of memory cells in the second cell array.
According to another aspect of the embodiments, when one of the plurality of memory cells in the first cell array is selected, the first, second, and third sense amplifier sections may be activated. When one of the plurality of memory cells in the second cell array is selected, the first, second and third sense amplifier sections may be activated.
According to another aspect of the embodiments, a third memory cell array may have the third sense amplifier section on a first side of the third memory cell array. A fourth sense amplifier section may be on an opposite side of the third memory cell array. When one of the plurality of memory cells in the second cell array is selected, the first, second, third, and fourth sense amplifier sections are activated.
According to another aspect of the embodiments, each bit line may include a complementary bit line pair. Adjacent bit line pairs connected to sense amplifiers in the first sense amplifier section may be separated by a plurality of bit lines that are connected to sense amplifiers in a sense amplifier section other than the first sense amplifier section.